The fabrication of various solid state devices employs semiconductor wafers on which semiconductor integrated circuits or other devices are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is a primary goal of semiconductor fabrication. After manufacturing, wafer “dies” having the integrated circuits are tested so that non-functional dies are identified. In order to detect defects on a wafer, electrical tests are used to thoroughly and accurately determine the existence and location of defects. The electrical tests may be conducted by simply determining whether the circuitry is functional or defective, and if defective, in what way is the circuitry defective.
In addition, a certain amount of retesting of the dies previously found to be defective is also conducted. When these dies are retested, many may be found to be operational during the second test pass, and are thus “recovered” to increase wafer yield. In traditional testing processes, all dies on a baseline wafer set are tested during a first test pass, and then the dies found to be defective are identified are typically retested to establish a recovery rate for certain types detected defects. Then, an engineer or other employee of the manufacturer manually determines which type of detected error is most worthwhile to retest. Specifically, the engineer would typically choose to retest only those types of defective dies that have a good history of recovery during the second test, for example, a 25% recovery rate or better. Unfortunately, manual selection for wafer reprobing is not always accurately accomplished, and mistakes may occur when resetting the testing equipment for reprobing. In addition, the expense of having an engineer handle the reprobing can be costly on the manufacturer.